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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Undervoltage and Overvoltage Protection
The device contains undervoltage and overvoltage pro-
tection features, and the flag bits can be found in the
Supply Event register (R0Ah and R0Bh, Table 12) and
the Watchdog register (R42h, Table 36). An internal V EE
undervoltage lockout circuit keeps the MOSFET off and
the device in reset until V AGND - V EE exceeds 28.5V for
more than 3ms. An internal V EE overvoltage circuit shuts
down the ports when V AGND - V EE exceeds 62.5V. The
digital supply also contains an undervoltage lockout that
triggers when V DD - V EE P 2V.
DC Disconnect Monitoring
The DC disconnect monitoring settings are found in the
Disconnect Enable register (R13h, Table 21). To enable
DC disconnect, set either the ACD_EN_ or DCD_EN_ bit
for the corresponding port to 1. To disable the DC discon-
nect monitoring, both the ACD_EN_ and DCD_EN_ bit for
that port must be set to 0. When enabled, if V RSENSE_
(the voltage across R SENSE_ ) falls below the DC load
disconnect threshold, V DCTH , for more than t DISC , the
device turns off power and asserts the DIS_ bit for the
corresponding port (R06h[7:4] and R07h[7:4], Table 10).
V DD Power Supply
The device has an internally regulated, 3.3V digital sup-
ply that powers the internal logic circuitry. V DD has an
undervoltage lockout (V DD_UVLO ) of 2V, and an under-
voltage condition on V DD keeps the device in reset and
the ports shut off. When V DD has recovered and the
reset condition clears, the VDD_UVLO bit in the Supply
Event registers is set to 1 (R0Ah[5] and R0Bh[5], Table
12). The digital address inputs, AUTO, and MIDSPAN
are internally pulled up to V DD , and all digital inputs are
referenced to DGND. V DD can also be used to source
up to 10mA for external circuitry. For internal regulator
stability, connect a 1.8k I resistor in parallel with a 33nF
capacitor at the V DD output (Figure 4). If an external
load is to be shared among multiple MAX5980 devices,
isolate the external supply bus with a series resistor (50 I
for 3 devices, 75 I for 4 devices), and place a single 1 F F
capacitor on the bus.
Hardware Power-Down
The EN digital input is referenced to DGND and is used
for hardware level control of device power management.
During normal operation, EN should be externally pulled
directly up to V DD , the 3.3V internal regulator output (see
the Typical Operating Circuit ).
To initiate a hardware reset and port power-down, pull
EN to DGND for at least 100 F s. While EN is held low, the
device remains in reset and the ports remain securely
powered down. Normal device operation resumes once
EN is pulled up to the V DD .
Thermal Shutdown
If the device's die temperature reaches +140 N C (typ),
an overtemperature fault is generated and the device
shuts down. The die temperature must cool down below
+120 N C (typ) to remove the overtemperature fault con-
dition. After a thermal shutdown condition clears, the
device is reset and the TSD event bit is set to a logical 1
(R0Ah[7]/R0Bh[7], Table 12).
Watchdog
The Watchdog register (R42h, Table 36) is used to
monitor device status, and to enable and monitor the
watchdog functionality. On a power-up or after a reset
condition, this register is set to a default value of 16h.
WD_DIS[3:0] is set by default to 1011, disabling the
watchdog timeout. Set WD_DIS[3:0] to any other value
to enable the watchdog. The watchdog monitors the
SCL line for activity. If there are no transitions for 2.5s
(typ), the WD_STAT bit is set to 1 and all ports are pow-
ered down (using the individual port reset protocol).
WD_STAT must be reset before any port can be reenabled.
I EXTERNAL P 10mA
V DD
R ISOLATION
EXTERNAL
3.3V BUS
MAX5980
DGND
1.8k I
33nF
1μF
EXTERNAL
BUS GND
Figure 4. V DD External Power Sourcing
21
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